1. Field of the Invention
The present invention relates generally to semiconductor memory devices having cylindrical capacitors, and more particularly to a semiconductor memory device having a cylindrical capacitor which is readily manufactured. The present invention further related to a method of manufacturing the same.
2. Description of the Background Art
Recently, demand for a semiconductor memory device has been rapidly expanding with the remarkable spread of information appliances such as a computer. Moreover, a large memory capacity and high speed operation are functionally requested. Technology has thus been developed in respect to high integration and high speed responsiveness or high reliability of a semiconductor memory device.
Among semiconductor memory devices, a DRAM is known in which memory information can be randomly inputted/outputted. A DRAM is generally comprised of a memory cell array which is a memory region for storing a multiple of information, and a peripheral circuitry required for communication between the memory region and outside.
FIG. 79 is a block diagram showing a general structure of a DRAM. In this figure, a DRAM 50 includes a memory cell array 51 for storing a data signal of information, a row and column address buffer 52 for externally receiving an address signal for selecting a memory cell constituting a storage circuit, a row decoder 53 and a column decoder 54 for decoding the address signal to designate the memory cell, a sense refresh amplifier 55 amplifying and reading a signal stored in the designated memory cell, a data-in buffer 56 and a data-out buffer 57 for inputting and outputting data, and a clock generator 58 generating a clock signal.
The memory cell array 51 occupying a large area on the semiconductor chip comprises a plurality of memory cells arranged in a matrix.
FIG. 80 is an equivalent circuit for four-bit memory cells. The memory cell shown is a so-called one transistor-one capacitor type memory cell comprised of a MOS transistor and a capacitor connected thereto. A memory cell of this type facilitates, because of its simple structure, enhancement of integration of a memory cell array, and thus, is often employed in a DRAM which requires a large capacity.
Memory cells of a DRAM can be classified into several types depending on the structure of a capacitor.
FIG. 81 is a cross sectional view of a conventional memory cell having a typical stacked type capacitor. Referring to FIG. 81, a memory cell includes a transfer gate transistor and a capacitor of a stacked type (hereinafter referred to as a stacked type capacitor). The transfer gate transistor includes a pair of source-drain regions 6, 6 formed in the surface of a silicon substrate 1, and a gate electrode (word line) 4 formed on the surface of the silicon substrate 1 through an insulating layer. The stacked type capacitor includes a lower electrode (storage node) 511 extending from an upper portion of the gate electrode 4 to an upper portion of a field isolation film 2, and having a part connected to one of the source-drain regions 6, 6, a dielectric layer 512 formed on the surface of the lower electrode 511, and an upper electrode (cell plate) 513 formed on the surface of the dielectric layer. A bit line 515 is connected to the other source-drain region 6 of the transfer gate transistor, through a bit line contact portion 516.
FIG. 82 is a plan view of a semiconductor memory device having a cylindrical capacitor, which belongs to another type of a DRAM and is disclosed in Japanese Patent Laid-Open No. 4-755. FIG. 83 is a cross sectional view taken along the line A--A in FIG. 82. Referring to these figures, a plurality of word lines 4a, 4b, 4c, 4d, 4e are formed on the surface of the silicon substrate 1. The bit lines 515 are formed crossing the word lines 4a, 4b, 4c, 4e at right angles. A memory cell is provided in the vicinity of the crossing point of the word line and the bit line.
The memory cell includes a transfer gate transistor 3 and a capacitor 10. The transfer gate transistor 3 includes a pair of the source-drain regions 6, 6 formed in the surface of the silicon substrate 1, and gate electrodes (word lines 4b, 4c) formed on the surface of the silicon substrate 1. An insulating layer 522 is provided over the silicon substrate 1 to cover the word lines 4b, 4c, 4d, 4e. A contact hole 514 for exposing one of the source-drain regions 6, 6 is provided in the insulating layer 522.
The storage node 511 is connected through the contact hole 514 to the source-drain region 6. The storage node 511 includes a first polycrystalline silicon layer 110a provided in contact with one source-drain region 6 through the contact hole 514, and along the surface of the insulating layer 522, a bottom conductive portion 511a provided thereon, and a sidewall conductive portion 511b provided along the periphery of the bottom conductive portion 511a, and extending upward.
A capacitor insulating film 512 covers the surface of the storage node 511. The cell plate 513 covers the outer surface of the storage node 511, with the capacitor insulating film 512 interposed therebetween. An interlayer insulating film 23 is provided over the silicon substrate 1 to cover the cell plate 513. A wiring layer 24 is formed over the interlayer insulating film 23. A passivation film 26 is provided on the silicon substrate 1 to cover the wiring layer 24.
A cylindrical capacitor thus constituted has its whole capacitance increased because the surface of the sidewall conductive portion 511b of the storage node 511 also contributes to the capacitance of the capacitor.
A method of manufacturing the semiconductor memory device shown in FIG. 83 will now be described.
FIGS. 84 to 98 are partial cross sectional views of the semiconductor device in respective steps in sequence of a manufacturing process of the semiconductor memory device shown in FIG. 83.
Referring to FIG. 84, the field oxide film 2 is formed in the main surface of the silicon substrate 1. The field oxide film 2 is formed utilizing a LOCOS method.
Referring to FIG. 85, after formation of a gate insulating layer 5 on the surface of the silicon substrate 1, the gate electrodes (the word lines 4b, 4c, 4d, 4e) of polycrystalline silicon are formed. The insulating layer 522 is formed to cover the word lines 4b-4e. Impurity ions are introduced in the surface of the silicon substrate 1 utilizing an ion implantation method, with the word lines 4b, 4c covered with the insulating layer 522 as mask, to form the source-drain regions 6, 6.
Referring to FIG. 86, a layer of refractory metal such as tungsten, molybdenum, titanium is deposited on the surface of the silicon substrate 1 (not shown), and patterned in a prescribed shape, thereby forming the bit line 515 directly contacted with one source-drain region 6 of the transfer gate transistor. An insulating layer 27 covers the bit line 515.
Referring to FIG. 87, a first polycrystalline silicon layer 110a having impurities introduced thereinto is deposited on or over the silicon substrate 1 utilizing a CVD method.
Referring to FIG. 88, an insulating layer 35 of silicon oxide film is deposited over the surface of the silicon substrate 1.
Referring to FIG. 89, a resist pattern 36 of a prescribed shape is formed on a surface of the insulating layer 35. The width of the resist pattern 36 defines a distance between capacitors adjacent to each other.
Referring to FIG. 90, the insulating layer 35 is selectively etched with the resist pattern 36 as a mask.
Referring to FIGS. 90 and 91, after removal of the resist pattern 36, a second polycrystalline silicon layer 110b having impurities introduced thereinto is deposited over the whole surface of the silicon substrate 1 utilizing the CVD method.
Referring to FIG. 92, a resist 37 is applied over the surface of the silicon substrate 1 to completely cover the uppermost surface of the second polycrystalline silicon layer 110b. Referring to FIGS. 92 and 93, the resist 37 is etched back so that a part of the second polycrystalline silicon layer 110b is exposed.
Referring to FIGS. 93 and 94, the exposed second polycrystalline silicon layer 110b is etched, and thereafter the insulating layer 35 is removed by etching. The storage node 511 is thus formed including the bottom conductive portion 511a and the sidewall conductive portion 511b.
Referring to FIGS. 94 and 95, by means of an isotropic etching, the exposed portion of the first polycrystalline silicon layer 110a is removed in a self-alignment manner, and thereafter the resist 37 is removed.
Referring to FIG. 96, the capacitor insulating film 512 formed of silicon nitride, silicon oxide, tantalum pentoxide, hafnium oxide, or the like is formed on the surface of the storage node 511.
Referring to FIG. 97, the cell plate 513 is formed to cover the outer surface of the storage node, with the capacitor insulating film 512 interposed therebetween. The cell plate 513 is formed with, for example, polycrystalline silicon having impurities introduced thereinto.
Referring to FIG. 59, the interlayer insulating film 23 is formed over the whole surface of the silicon substrate 1 to cover the cell plate 513. The wiring layer 24 a prescribed shape is formed on the interlayer insulating film 23. The passivation film 26 is formed over the whole surface of the silicon substrate 1 to cover the wiring layer 24.
A method of manufacturing a cylindrical capacitor previously proposed is constituted as described above, and has the following problems. FIG. 99A is a plan view of the semiconductor device shown in FIG. 92. FIG. 99A shows a state in which the whole surface of the silicon substrate 1 is covered with a resist before etch back of the resist. A shaded portion is the resist 37. Referring to these figures, no significant difference is noticed between the area of the resist 37 before etch back (see FIG. 99A) and the area of the resist 37 after etch back (see FIG. 99B). Although etch back was effected, the resultant small change of the area made it difficult to detect the end of the etch back. Consequently, a problem that the manufacturing method shown in FIGS. 84 to 98 could not be easily implemented arose.